Certain embodiments of the invention relate to the testing of embedded devices. More specifically, certain embodiments relate to a software programmable verification tool having a built-in self-test (BIST) for testing and debugging multiple memory modules in an embedded device under test (DUT).
Advancement in chip technology has resulted in the development of embedded processors and controllers. Embedded processors and/or controllers may include microprocessor and/or microcontroller circuitry that have been integrated into a single package containing associated companion logic and peripherals. Embedded processors differ from microprocessors and microcontrollers in that microprocessors and microcontrollers are typically coupled with associated logic on a circuit board to implement a specified application.
Further advancements in chip technology have increased packaging density to the point where it is now possible to implement a standalone application on a single chip. In this regard, the resulting integrated circuit (IC) is called a system on a chip (SoC). A SoC may include one or more microprocessor and/or microcontroller elements, peripherals, associated logic and memory all fabricated on a densely packaged IC. For example, a SoC for a broadband set-top box may include a receiver, a transmitter, a digital signal processor, one or more encoders and decoders, random access memory (RAM), and non-volatile memory (NVM), all of which may be integrated on a single chip. The peripherals are typically called embedded peripherals. In the case of a memory element, the memory element may be called an embedded memory.
Notwithstanding, these advancements in chip technology are not without their challenges. Chip testing is crucial to design, development, manufacture and integration phases. Chip density, has and in some cases, almost eliminated the use of traditional chip testing methods. For example, many embedded systems utilize multiple layers of epoxy having conduits and lines buried deep within, making them practically inaccessible to external debugging and verification tools. Additionally, traditional methods such as capturing traces using an oscilloscope may be problematic for many embedded processors that either operate at or have bus speeds in excess of a few hundred megahertz (MHz).
Although techniques such as boundary-scan have been developed to address some of these problems, boundary scan may not be a practical solution in embedded systems, for example embedded memories, where real estate is extremely expensive and in which embedded system components are densely packed. Boundary-scan typically includes embedding at least one test access port (TAP) and associated circuitry into an embedded system to facilitate tasks such as testing debugging, and verification. For example, the Institute of Electronic Engineers (IEEE) joint test action group (JTAG) TAP or IEEE 1149.1 standard utilizes boundary-scan for debugging and verifying embedded systems.
Furthermore, as the cost of memory continues to decline, increased packaging density technology has resulted a proliferation of embedded systems with large amounts of memory. Especially in cases where there is no direct connection between embedded memory module pins and the package pins, external testing may be extremely difficult if not impossible. Attempts to use complex and often convoluted test vectors are extremely time consuming and typically result in increased chip cost.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.